This invention relates to hotsocket detection circuitry, and more particularly, to hotsocket detection circuitry for integrated circuits such as programmable logic device integrated circuits.
Integrated circuits such as programmable logic devices have data pins and power pins. The data pins are coupled to input-output circuits that are typically located around the periphery of a chip. Data pins are used to convey data signals to and from the input-output circuits. The power pins on an integrated circuit chip are used to supply power supply voltages to core logic on the chip and to the input-output circuits.
The pins on an integrated circuit are often used to form communications ports. Commonly-used ports include ports that support standards such as the universal serial bus (USB) standard, the Firewire standard (IEEE 1394), etc. Electronic components that use these ports are often designed to be hot swappable. A hot-swappable component can be inserted into a system or removed from a system without powering down the system.
When a hot-swappable peripheral is connected to a powered port, it is not known in advance which pins in the port will be the first to make electrical contact with each other. If a user inserts a peripheral in one way, the power pins in the port may be the first to be electrically connected with each other. If, however, the user inserts the peripheral in a slightly different way, the data pins may be the first to make electrical contact with each other. This type of uncertainty about the order in which the data and power pins are connected must be taken into account when designing integrated circuits for hot swappable applications. For example, such circuits should be designed to avoid circuit failures in situations in which the data pins of the integrated circuit receive signals before the power supply pins have received power and before the circuits of the integrated circuit have had an opportunity to be properly powered up and establish normal operating conditions.
To provide tolerance to hot swapping, integrated circuits such as programmable logic devices may be provided with hotsocket detection circuitry. The hotsocket detection circuitry turns off output buffers within the input-output circuitry during power-up and power-down operations. This ensures that the input-output circuits are not powered up until the core logic is ready for normal operation.
Power-on-reset circuitry can be used to control the operation of the core logic. The power-on-reset circuitry monitors the power supply voltages that are received through the input-output pins. When the power supply voltages reach their normal operating levels, the power-on-reset circuitry generates an appropriate power-on-reset signal. The core logic can be allowed to operate normally upon receiving this power-on-reset signal.
Once the core logic is operating normally and the power supply voltages are fully powered, the hotsocket detection circuitry can produce a hotsocket signal that enables the output buffers and allows the input-output circuitry to function normally.
Due to fabrication process variations, the transistors in the power-on-reset circuitry and hotsocket detection circuitry on an integrated circuit may exhibit performance fluctuations. It may be desirable to minimize performance fluctuations in the power-on-reset circuitry using a process-tolerant design. However, the use of conventional hotsocket detection circuitry in integrated circuit environments that have process-tolerant power-on-reset circuitry may lead to undesirable situations in which the hotsocket detection circuitry enables the input-output circuitry before the power-on-reset circuitry enables the core logic. This can lead to circuit damage or signal corruption.
It would therefore be desirable to be able to provide improved hotsocket detection circuitry for use on integrated circuits such as programmable logic devices.